The present invention relates to a method of making a field effect transistor, and more particularly, to a method of making a field effect transistor for high frequency.
It is generally advantageous for a field effect transistor (hereinafter, FET) for high frequency (GHZ band) to comprise a gate having a submicron length to reduce noises.
Referring to FIG. 1, a conventional metal semiconductor field effect transistor (MSFET) is illustrated having a T-shaped gate(or a mushroom-shaped gate).
High speed FETs for low noises such as a GaAs FET and a high electron mobility transistor have the structure shown in FIG. 1, to lower a resistance value of the gate and to reduce a length of the gate.
In FIG. 1, reference numeral 1 denotes a GaAs substrate, reference numeral 2 denotes an n-type GaAs layer, reference 3 denotes a T-shaped gate, reference numeral 4 denotes a source, reference numeral 5 denotes a drain, and symbol L denotes a length of the gate 3.
Conventionally, as patterning methods for forming the T-shaped gate, a photolithography method utilizing a light and an electron beam lithography method utilizing an electron beam have been used.
The photolithography method and the electron beam lithography method have been most widely used upon the performance of patternings during the manufacturing process of a semiconductor device.
The photolithography method is, for example, a technique in which ultraviolet rays are irradiated on a photoresist (PR) through a mask having a pattern comprising a transparent portion and an opaque portion to expose the PR. Then, the exposed PR is developed to obtain a desired PR pattern.
The photolithography method can achieve a submicron pattern having a line-width of about 0.5 .mu.m and also process a number of wafers per unit time since a patterning process is carried out by merely one exposure process which uses ultraviolet rays. Accordingly, this method is advantageous in mass production.
On the other hand, the electron beam lithography method can achieve a submicron pattern having a line-width of about 0.1 .mu.m since this method uses electrons having a characteristic, of a relatively smaller beam spot size as compared to light such as ultraviolet rays. Therefore, this method is widely used for researching super high devices such as GaAs FET.
However the electron beam lithography method has disadvantages in that it has a rate of production relatively lower than that of the photolithography method since all patterns are depicted one by one with an electron beam having a small spot size. The electron beam lithography method has been used to form a T-shaped gate having a submicron length of less than 0.5 .mu.m.
Referring to FIGS. 2a and FIG. 2b, a method for manufacturing a T-shaped gate is illustrated.
As shown in FIG. 2a, first, an electron beam resist(hereinafter, E-beam resist) 11 having a low electron-sensitivity, an E-beam resist 12 having a high electron-sensitivity, and an E-beam resist 13 having a low electron-sensitivity are coated on a substrate 10, in this order. Thereafter, the E-beam resists 11, 12, and 13 are exposed by an electron-beam.
At this time, the E-beam resist 11 contacting the substrate 10 and having a low electron-sensitivity is less exposed than the E-beam resist 12 having a high electron-sensitivity. As shown in FIG. 2a, the E-beam resist 12 is exposed over a region wider than a region which is irradiated by the E-beam, due to a back-scattering phenomenon caused by the substrate 10. Thereafter, the above E-beam resists 11, 12, and 13 are subjected to a development process, to obtain the E-beam resist patterns 11a, 12a, and 13a shown in FIG. 2b.
It is possible to advantageously perform a lift-off process for removing unnecessary metal layers since the E-beam resist 13 having a low electron-sensitivity is formed as the upper most layer. Subsequently, a metal is deposited to form a T-shaped gate 14, as shown in FIG. 2b. Then, a lift-off process is carried out to remove the unnecessary metal layers 14a and the E-beam resist pattern 13a.
As above mentioned, the photolithography method cannot obtain a pattern having a submicron length of less than 0.5 .mu.m. However, this method is chiefly used to produce FETs having a T-shaped gate in great quantities.
Referring to FIGS. 3a through 3d, a method is illustrated where a FET having a T-shaped gate is manufactured using the photolithography method.
First, a source 21 and a drain 22 are formed on each edge of a substrate 20, respectively, as shown in FIG. 3a. As shown in FIG. 3b, an insulation film and a photoresist are formed on the substrate 20, the source 21 and the drain 22, in this order.
The photoresist is coated with a mask and then is subjected to an exposure process and a development process to obtain a photoresist pattern 24 corresponding to a gate length. Subsequently, the insulation film and the substrate 20 is subjected to a wet-etching process using the photoresist pattern 24 as an etch mask.
Accordingly, a portion of the insulation film and a portion of the substrate 20 corresponding to the gate length L are removed to form a groove having a width wider than the gate length L in the surface of the substrate 20. That is, the substrate 20 is etched with a width wider than that of the insulation film pattern 23, due to the wet-etching process.
Subsequently, the photoresist pattern 24 is removed and then a photoresist 25 having a high photo-sensitivity and a photoresist 26 having a low photo-sensitivity are formed on the insulation film pattern 23, in this order, as shown in FIG. 3c. Thereafter, a mask is coated on the photoresist having a low photo-sensitivity. Then, the photoresists are subjected to an exposure process and a development process. At this time, a portion of the photoresist 26 having the low photo-sensitivity is removed by a width wider than the gate length L and a portion of the photoresist 25 having the high photoresist is by a width wider than the width of the removed portion of the photoresist 26 having the low photosensitivity, as shown in FIG. 3c. Accordingly, photoresist patterns 25 and 26 are formed. Subsequently, a metal is deposited to form a gate. As a result, a T-shaped gate 27 is formed over the insulation film pattern 23, and simultaneously an unnecessary metal layer 27a is formed on the photoresist pattern 26. Then, the photoresist patterns 25 and 26 and the unnecessary metal layer 27a are removed using a lift-off process, as shown in FIG. 3d.
The device manufactured by FIGS. 3a to 3d is called a metal semiconductor junction field effect transistor (MSJFET).
However, the above-mentioned conventional patterning method has the following problems.
First, the conventional E-beam lithography method can process wafers at only 4-5 sheets per hour since all patterns should be depicted with an electron-beam having a small spot size. Accordingly, this method is improper for mass production due to the low throughput.
Second, in the conventional photolithography method, it is impossible to achieve the high integration of FET since a submicron pattern of less than 0.5 .mu.m cannot be formed.
This method also requires two sheets of mask to form a T-shaped gate as shown in FIG. 3a to FIG. 3d and also requires double the number of critical mask-arrangement processes thereby deteriorating the production rate of FET and increasing the manufacturing cost.